1. Technical Field
The present invention relates to a decoding circuit for a wafer burn-in test, and in particular to a decoding circuit for a wafer burn-in test that internally generates a strobe signal by using external input address signals for the wafer burn-in test.
2. Description of the Related Art
A conventional decoding circuit for a wafer burn-in test receives a strobe address signal for generating a strobe signal and a plurality of input address signals for controlling a decoding operation in the wafer burn-in test. The number of input pins required on a conventional decoding circuit corresponds to the sum of the number of the strobe address signals and the number of the input address signals. Accordingly, as the number of input addresses increase, the area for the input pad containing the input pins also increases, thereby increasing the whole layout area of a semiconductor memory device. In consideration of the relatively large area of the input pad in a typical semiconductor memory device, the number of decoding circuit input pads must be decreased in order to reduce the whole layout area.
Referring to FIG. 1, a conventional decoding circuit for a wafer burn-in test is illustrated. As described, the conventional decoding circuit for the wafer burn-in test includes an address control unit 10, a strobe signal generating unit 20 and a decoding unit 30.
In general, the address control unit 10 logically operates external input address signals ADD less than 8 greater than , ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than  and a test signal WBI, and generates address signals AWB less than 8 greater than , AWB less than 9 greater than , AWB less than 11 greater than  and AWB less than 12 greater than . In addition, the address control unit 10 buffers the address signals AWB less than 9 greater than , AWB less than 11 greater than  and AWB less than 12 greater than , and generates address signals AWD less than 9 greater than , AWD less than 11 greater than  and AWD less than 12 greater than .
The strobe signal generating unit 20 receives the strobe address signal AWB less than 8 greater than , and generates a strobe signal VCMDP.
The decoding unit 30 receives the address signals AWBD less than 9 greater than , AWD less than 9 greater than , AWBD less than 11 greater than , AWD less than 11 greater than , AWBD less than 12 greater than  and AWD less than 12 greater than  from the address control unit 10 and the strobe signal VCMDP from the strobe signal generating unit 20, and decodes the received signals. In addition, the decoding unit 30 selectively outputs an all word line driving signal ALL, an even word line driving signal EVEN, an odd word line driving signal ODD, word line driving signals 2RBE and 2RBO and a sense amp driving signal SAE according to the decoding result.
In detail, the address control unit 10 includes NOR gates NOR1-NOR4 for respectively NORing the strobe address signal ADD less than 8 greater than , the input address signals ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than , and the test signal WBI. Inverters IV1-IV4 delay and logically non-reverse the output from the NOR gate NOR1 and output the address signal AWB less than 8 greater than . Inverters IV5-IV8 delay and logically non-reverse the output from the NOR gate NOR2 and output the address signal AWB less than 9 greater than . Inverters IV9-IV12 delay and logically non-reverse the output from the NOR gate NOR3 and output the address signal AWB less than 11 greater than . Inverters IV13-IV16 delay and logically non-reverse the output from the NOR gate NOR4 and output the address signal AWB less than 12 greater than . Inverters IV17-IV19 delay and logically non-reverse the address signal AWB less than 9 greater than  and output the address signal AWD less than 9 greater than . Inverters IV20-IV22 delay and logically non-reverse the address signal AWB less than 11 greater than  and output the address signal AWD less than 11 greater than . Inverters IV23-IV25 delay and logically non-reverse the address signal AWB less than 12 greater than  and output the address signal AWD less than 12 greater than .
The strobe signal generating unit 20 includes inverters IV26-IV32 for delaying and logically non-reversing the address signal AWB less than 8 greater than , and inverters IV33-IV37 for delaying and logically non-reversing the output from the inverter IV32. A NAND gate ND1 NANDs the output from the inverter IV32 and the output from the inverter IV37. A NAND gate ND2 NANDs the output from the NAND gate ND1 and an inputted power up signal PWRUP, and outputs the strobe signal VCMDP.
Finally, the decoding unit 30 includes NAND gates ND3-ND10 for respectively NANDing the address signals AWBD less than 9 greater than , AWD less than 9 greater than , AWBD less than 11 greater than , AWD less than 11 greater than , AWBD less than 12 greater than  and AWD less than 12 greater than  from the address control unit 10, and inverters IV38-IV45 for respectively inverting the outputs from the NAND gates ND3-ND10. NAND gates ND11-ND18 respectively NANDs the outputs from the inverters IV38-IV45 and the strobe signal VCMDP from the strobe signal generating unit 20. An NMOS transistor N1 receives the power up signal PWRUP inverted by an inverter IV46, and outputs a ground voltage VSS to NAND gates ND19-ND32 composed of a latch. Inverters IV47-IV60 respectively delay the outputs from the NAND gates ND19-ND32, and output the all word line driving signal ALL, the even word line driving signal EVEN, the odd word line driving signal ODD, the word line driving signals 2RBE and 2RBO and the sense amp driving signal SAE.
The conventional decoding circuit for the wafer burn-in test includes the strobe address signal ADD less than 8 greater than  as a first address group for generating the strobe signal VCMDP during the wafer burn-in test, and the input address signals ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than  as a second address group for selectively enabling the word line driving signals during the wafer burn-in test.
Referring now to FIG. 2, an operational timing view of the conventional decoding circuit for the wafer burn-in test is shown. When the test signal WBI is enabled during the wafer burn-in test, the strobe address signal ADD less than 8 greater than  is enabled, and then the strobe signal VCMDP is generated. When the strobe signal VCMDP is generated from the strobe signal generating unit 20, the decoding unit 30 decodes the address signals AWBD less than 9 greater than , AWD less than 9 greater than , AWBD less than 11 greater than , AWD less than 11 greater than , AWBD less than 12 greater than  and AWD less than 12 greater than  from the address control unit 10. In addition, while the input address signals ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than  are simultaneously enabled in a high level, a reset pulse RESETBP is generated at the point when the strobe signal VCMDP is generated.
However, the conventional decoding circuit for the wafer burn-in test needs the strobe address signal ADD less than 8 greater than  for generating the strobe signal VCMDP and the plurality of input address signals ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than  to perform the wafer burn-in test. Accordingly, the conventional decoding circuit for the wafer burn-in test requires a special pad for receiving the strobe address signal add less than 8 greater than ADD less than 8 greater than  of controlling generation of the strobe signal VCMDP as well as a pad for receiving the external input address signals ADD less than 9 greater than , ADD less than 11 greater than  and ADD less than 12 greater than . As a result, the area of the input pads is increased according to the number of pad is increased and thus the whole layout area of the semiconductor memory device is also increased.
A decoding circuit for a wafer burn-in test may include: an address control unit for buffering a plurality of externally inputted address signals and generating a plurality of internal address signals in order to selectively enable word line driving signals during the wafer burn-in test; a strobe signal generating unit for generating a plurality of delay pulse signals having a predetermined pulse width according to the plurality of address signals, and generating a strobe signal by logically operating the plurality of delay pulse signals wherein each delay pulse signal is enabled when its corresponding address signal inputted externally is transited, and the strobe signal has a pulse when at least one delay pulse signal is enabled; and a decoding unit for decoding the plurality of internal address signals according to the strobe signal from the strobe signal generating unit, and selectively outputting the word line driving signals.